The field of the invention is digital electronics.
Implementation of complicated Boolean expressions can be accomplished by a number of methods utilizing one or more integrated circuits (ICs). One such method involves the use of numerous AND-OR logic or NAND combinational logic circuits. Another method involves the use of specialized ICs such as Programmable Logic Array (PLA) devices. Yet another method involves using a data selector where the data inputs of the data selector have logic levels corresponding to the output column of a truth table defining the function to be implemented, and where the data select values of the data selector have logic values corresponding to the input values of the function. Another method, similar to the use of a data selector, involves the use of a memory device to act as a look up table (LUT) where the values of the output column of a truth table defining the function are stored in the memory device and the inputs to the function are used to specify the address of a particular value in the LUT.
The use of numerous AND-OR logic or NAND combinational logic circuits is problematic in that logic circuits must be added, removed, and/or rewired whenever a new expression is to be implemented. Similarly, many PLA devices are not modifiable, or are only modifiable via physical removal of the PLA device. These methods are thus unsuitable for use in applications where the expression being implemented must be changed frequently or quickly.
The use of a data selector is problematic in that the number of data inputs to the selector is exponentially related to the number of function inputs. If one wanted to implement the simple expression A+B+C where A and B and C are each N bit values where N is 32, the data selector would need to have 3*32=96 data select inputs and 2(3*32)=7.9228xc3x971028 data input applying logical expressions to values involving a large number of bits, the use of a data selector is impractical due to the extremely large number of data input lines required. The use of a memory device implementing a LUT is similarly problematic due to the large number of storage locations required. Moreover, LUTs require additional time to be initialized or xe2x80x9cprogrammedxe2x80x9d which slows down the implementation process. The implementation process is slowed even further if devices utilizing LUTs do not have an input line for every value in the table.
Thus there is a continuing need to develop new integrated circuits which are capable of implementing Boolean expressions with a minimal number of input lines and a little or no internal storage.
A programmable arithmetic and logic unit (ALU) comprising a plurality of data selectors, the data selectors having corresponding data input lines; a plurality of ALU function input lines wherein the number of ALU function input lines is equal to the number of data input lines on each of the data selectors, and each ALU function input line corresponds to one data input line on each of the data selectors; wherein each of the data input lines of each of the data selectors is connected to the corresponding data input lines of each of the other data selectors and to the corresponding ALU function input line.
Various objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of preferred embodiments of the invention, along with the accompanying drawings in which like numerals represent like components.